The present invention generally relates to electronic circuits and methods and, more specifically, to a circuit and a method that provide glitch suppression.
A glitch is a short and unwanted signal or condition in an electronic circuit. When a glitch occurs, the electronic circuit may react in an undesirable or unpredictable manner. Accordingly, electronic circuits are generally designed to minimize the impact of glitches, either by predicting when glitches will occur and ignoring them, or by actively suppressing the glitches.
Although many types of electronic circuits are susceptible to glitch interference, the first-in, first-out (FIFO) memory device is particularly susceptible to glitches. A FIFO is an electronic circuit configured as a read-write memory. It is commonly used as a buffer to smooth the flow of data in a digital data stream. The output data are in the same order or sequence as the input data.
The FIFO circuit is particularly useful for transferring data between two circuits operating on different clocks. For example, a communication circuit may be operating at a communication clock speed and providing communication data. It may be desired to pass the communication data into a processor. However, the processor is typically operating at a processor clock speed. A FIFO circuit may be arranged to accept the communication data at the communication clock speed and send that same data to the processor at the processor speed.
Generally, the FIFO circuit includes a memory bank having many individual memory registers, each having a unique address. For example, the memory bank may be a few bytes deep or thousands of bytes deep depending upon specific applications. In operation, the FIFO memory bank accepts data under the control of memory write logic. The memory write logic writes incoming data into the memory registers at the next available address location. Simultaneously, memory read control logic is used to determine which data will be read and output from the FIFO. More specifically, the write control logic and the read control logic each have a pointer for tracking address location. Typically, these pointers are implemented as counters which increment through the available addresses of the memory device. Once a counter reaches the last available memory location in the memory, the pointer resets to the 0 location. For example, if a FIFO has 256 memory addresses, the counter will increment from 0 to 255 and then reset to 0 on the next increment. In such a manner, the 256 memory address FIFO can hold only 256 unread data points at one time. If more data is to be retained, a FIFO having a larger memory bank is needed.
Since the available memory registers are limited by the size of the memory bank, the FIFO device has logic for controlling when reads and writes may be made to the FIFO device. Typically, such control logic uses flag signals for indicating memory conditions within the FIFO. Without such flag control logic, the FIFO may not operate in an efficient and reliable manner. For example, if the incoming data is being written quickly into the FIFO memory bank, but the read circuit is operating more slowly, without a flag control the write circuit could overrun the read circuit. In such a manner, data would be lost or corrupted. More specifically, if the FIFO memory has all memory registers filled with data that has not yet been read by the read-circuit, and the write circuit is allowed to write into the memory, a memory location will be replaced without that data having been read by the read circuit. The data that was written over is thereby irrecoverably lost. Therefore, if the FIFO memory is full of unread data, the FIFO circuit provides for a flag which disables the ability of the write-control logic to write into the memory until a read function has enabled a free memory location to become available.
Referring to FIG. 6, a conventional flag control logic 200 is illustrated. The write-control logic 200 generally comprises a write pointer 202 and a read pointer 204. The values of the write pointer and a read pointer are compared by comparator 206. If the write pointer and the read pointer are compared and have the correct relationship, then a flip-flop 208 is set. The output of the flip-flop is a flag signal 209 which is then used to enable or disable memory control logic or otherwise affect system-wide logic. For example, if flag 209 is defined to be a full-flag indicating that the memory bank is full, then when the write pointer 202 is equal to the read pointer 204, the comparator 206 will cause the flip-flop 208 to set the flag 209. When the flag 209 is set, the write logic will be disabled so that no more data can be written to the FIFO memory until an additional read has been made.
Referring to FIG. 7, a timing diagram 220 for the flag logic of the conventional FIFO circuit is illustrated. The timing diagram 220 shows a write clock 222 and a read clock 224 operating asynchronously. A write pointer 226 and a read pointer 228 increment on each sequential write or read to the memory bank, respectively. A compare signal 230 is also provided which indicates when the read pointer and write pointer are in a particular relationship. The compare signal is enabled to the write clock 222 to set the flag 232 which is provided in the form of a D flip-flop.
As illustrated in FIG. 7, the comparator makes constant comparison between the write pointer 226 and the read pointer 228. If the compare circuitry is configured to identify the relationship of the write pointer 226 being equal to the read pointer 228, then the compare signal 230 should only be activated when the write pointer 226 is equal to the read pointer 228. For example, at location 234 the write pointer is set to 100 and the read pointer is set to 100, therefore the compare circuit is set high. Since the compare circuit is high, indicating that the full relationship exists in the FIFO memory, the flag 232 is also set so that the write logic is disabled. In such a manner, no more data will be written to the FIFO memory until additional reads occurred. For example, at position 236 an additional read occurs, setting the read pointer to 101; since the write pointer 226 and the read pointer 228 are no longer equal, the compare signal 230 transitions low. Synchronously with the write clock 222, the flag is removed, thereby enabling additional writes to the memory.
To avoid generating glitches in the compare line 230, the write pointer and the read pointer have counters utilizing a counting scale in which the sequential numbers differ in only one bit. An often used code is the Gray code, which provides a sequence of digital data where only one bit changes for each increment of the code. For example, the read pointer 228 is shown to go through a progression where after each read only one bit in the three-bit digital representation changes. Since only one bit changes at each increment, the risk of generating a glitch is substantially reduced.
Using a counting sequence such as the Gray code is typically difficult to implement unless the relationship between the write pointer and the read pointer is predefined. For example, the Gray code must be decoded into a format that enables the numerical difference between codes to be determined. Although it may be possible to provide decoding logic or a look-up table, the decoding process would undesirably slow the throughput of the overall FIFO circuit.
It would be highly desirable to permit the memory relationship between the read pointer and the write pointer to be programmable. In such a manner, the specific function of a flag could be adjusted for application specific purposes. To efficiently implement a programmable flag, the pointers are preferably implemented as regular binary numbers following the regular binary progression. As an illustration, FIG. 8 shows a timing diagram 240 in which the write pointer 242 and the read pointer 244 are implemented using regular binary counters. As before, the compare line 246 goes high when the write pointer 242 is equal the read pointer 244. For example, at location 249, the write pointer 242 is equal to the read pointer 244, and therefore the compare line 246 is high, and the flag 248 is set to disable further writes into memory.
However, when the read pointer 244 transitions from 001 to 010, an increment of one, there are two bits in the read pointer 244 that change. Because of the uncertainty in the value of the read pointer 244 as two bits change, a glitch 250 may be generated on the compare line 246. If the glitch occurs substantially synchronous with the write clock 222, then the full flag 248 will be set at location 252. Accordingly, during time period 254 the FIFO circuit may not allow any additional writes into FIFO memory, even though memory spaces are available. Thus, glitches in a FIFO circuit may lead to false flag conditions which cause inefficiencies and inaccuracies in the operation of the FIFO circuit. Therefore, there is a need to efficiently provide glitch suppression in a way that enables programmable flags.
It is therefore an object of the present invention to provide a circuit for efficient glitch suppression. It is another object of the present invention to provide glitch suppression in a manner that facilitates programmable flag logic. To overcome the deficiencies in the conventional circuits and methods and to achieve at least the stated objectives, a glitch suppression circuit and method are provided.
The glitch suppression circuit may include a read pointer and a write pointer that track memory locations. A comparator compares the read pointer and the write pointer and provides a compare signal indicative of a particular memory condition. The glitch suppression circuit may include an offset read pointer and an offset write pointer that track memory locations. An offset comparator compares the read pointer and the write pointer and provides an offset compare signal indicative of the particular memory condition. A timing signal controls a multiplexer for selecting either the compare signal or the offset compare signal to set a logic flag. The setting of the logic flag may be synchronized to a timing signal.
Advantageously, the disclosed flag logic enables the use of programmable flags for a memory device, including a FIFO device. Even with programmable flags, the resulting memory device is enabled to suppress the effect of glitches while operating at an efficient throughput rate. Accordingly, the memory device avoids the detrimental effect of glitches while still enabling efficient operation.
These and other features and advantages of the present invention will be appreciated from review of the following detailed description of the invention, along with the accompanying figures in which like reference numerals refer to like parts throughout.